Synchronous Counter Code for Xilinx FPGA

Verilog Code

module countersync(reset, Q, clock);
input reset;
input clock;
output [3:0]Q;
reg[3:0]Q;

always @ (posedge clock)
if(!rst)Q<=0; else Q<=Q+1; endmodule

Testbench Code

module testbench;
reg reset,clock;
wire [7:0]Q;
parameter STEP=60;


// Instantiate the module
countersync instance_name (
.reset(reset),
.Q(Q),
.clock(clock)
);

always#(STEP/2)clk=~clk;
initial begin
clock=1;reset=0;#(STEP-10);
reset=1;#(STEP*20);
$stop;
end
endmodule