FSM Code for Xilinx FPGA

Verilog Code (for sequence 0010)

module sequence(x, clock, reset, y, Q);
input x;
input clock;
input reset;
output y;
reg y;
output [2:0]Q;

parameter start=3'b000;
parameter got0=3'b001, got00=3'b010, got001=3'b011, got0010=3'b101;
reg[2:0]Q; //state variable
reg[2:0]D;

//next state logic
always @(x or Q)
begin
case (Q)
start: D=x ? start:got0;
got0: D=x ? start:got00;
got00: D=x ? got001:got0;
got001: D=x ? start:got0010;
got0010: D=x ? start:got00;
default: D=3'bxxx;
endcase
end

always @ (posedge clock)
begin
if(reset)
Q=D;
else
Q=0;
end

//output logic
always @ (Q)
y=Q[2];
endmodule

Testbench Code

module testbench;
reg x;
reg clock;
reg reset;
wire y;
wire [2:0]Q;

// Instantiate the module
sequence instance_name (
.x(x),
.clock(clock),
.reset(reset),
.y(y),
.Q(Q)
);

always #100
clock=~clock;

//input data bit
initial begin
clock=1; x=0; reset=0; #200
x=0; reset=0; #200
x=0; reset=0; #200
x=1; reset=0; #200
x=0; #200
x=0; #200
x=1; #200
x=0; #200
x=0; #200
x=1; #200
x=0; #200
$stop;
end
endmodule