4-bit Parallel Full Adder Code for Xilinx FPGA

Verilog code

module fulladder(x0, x1, x2, x3,cin,c, y0, y1, y2, y3, s0, s1, s2, s3);
input x0, x1, x2, x3; //Four bit input X
input y0, y1, y2, y3; //Four bit input Y
input cin; //Carry input
output c; //Carry output
output s0,s1,s2,s3; //Sum output

wire s10,s20,s30,s40,c10,c11,c0,c20,c21,c1,c30,c31,c2,c40,c41; //Intermediate nodes

xor V1(s10,x0,y0); // x0 xor y0 = s10
xor V2(s0,s10,cin); // s10 xor cin = s0
and V3(c10,x0,y0); // x0 and y0 = c10
and V4(c11,s10,cin); // s10 and cin = c11
or V5(c0,c10,c11); // c10 or c11 = c0

xor V6(s20,x1,y1);
xor V7(s1,s20,c0);
and V8(c20,x1,y1);
and V9(c21,s20,c0);
or V10(c1,c20,c21);

xor V11(s30,x2,y2);
xor V12(s2,s30,c1);
and V13(c30,x2,y2);
and V14(c31,s30,c1);
or V15(c2,c30,c31);

xor V16(s40,x3,y3);
xor V17(s3,s40,c2);
and V18(c40,x3,y3);
and V19(c41,s40,c2);
or V20(c,c40,c41);

endmodule


Testbench code

`timescale 1ns/1ns
module testbench;
reg x0, x1, x2, x3, x0, x1, x2, x3, cin; // Inputs
wire c,s0,s1,s2,s3; // Outputs


// Instantiate the module
fulladder instance_name (
.x0(x0),
.x1(x1),
.x2(x2),
.x3(x3),
.y0(y0),
.y1(y1),
.y2(y2),
.y3(y3),
.cin(cin),
.c(c),
.s0(s0),
.s1(s1),
.s2(s2),
.s3(s3)
);

initial begin

x0=0; x1=0; x2=1; x3=1; y0=1; y1=1; y2=0; y3=0; cin=0; #250;
x0=1; x1=0; x2=0; x3=0; y0=0; y1=0; y2=1; y3=0; cin=1; #250;
x0=1; x1=1; x2=1; x3=1; y0=1; y1=0; y2=1; y3=1; cin=1; #250;
x0=1; x1=0; x2=0; x3=1; y0=0; y1=1; y2=0; y3=0; cin=1; #250;
$stop;
end
endmodule