8-bit Shift Register Code for Xilinx FPGA

Verilog Code

module shiftres(w, clock, Q);

input w;
input clock;
output [1:8]Q;
reg [1:8]Q;

always @(posedge clock) //Shift Resistor logic start
begin
Q[8]<=w; // Value of w count as Q[8]
Q[7]<=Q[8]; //Value shifted from Q[8] to Q[7]
Q[6]<=Q[7]; //Value shifted from Q[7] to Q[6]
Q[5]<=Q[6]; //Value shifted from Q[6] to Q[5]
Q[4]<=Q[5]; //Value shifted from Q[5] to Q[4]
Q[3]<=Q[4]; //Value shifted from Q[4] to Q[3]
Q[2]<=Q[3]; //Value shifted from Q[3] to Q[2]
Q[1]<=Q[2]; //Value shifted from Q[2] to Q[1]
end
endmodule

Testbench Code


module testbench;
reg w, clock;
wire [1:8]Q;

// Instantiate the module
shiftres instance_name (
.w(w),
.clock(clock),
.Q(Q)
);

always#100
clock=~clock;
initial begin
clock=1; w=1; #200
w=0; #200
w=1; #200
w=0; #200
w=0; #200
w=1; #200
w=1; #200
w=0; #200
$stop;
end
endmodule