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module countersync(reset, Q, clock);
input reset;
input clock;
output [3:0]Q;
reg[3:0]Q;
always @ (posedge clock)
if(!rst)Q<=0; else Q<=Q+1; endmodule
module testbench;
reg reset,clock;
wire [7:0]Q;
parameter STEP=60;
// Instantiate the module
countersync instance_name (
.reset(reset),
.Q(Q),
.clock(clock)
);
always#(STEP/2)clk=~clk;
initial begin
clock=1;reset=0;#(STEP-10);
reset=1;#(STEP*20);
$stop;
end
endmodule
module sequence(x, clock, reset, y, Q);
input x;
input clock;
input reset;
output y;
reg y;
output [2:0]Q;
parameter start=3'b000;
parameter got0=3'b001, got00=3'b010, got001=3'b011, got0010=3'b101;
reg[2:0]Q; //state variable
reg[2:0]D;
//next state logic
always @(x or Q)
begin
case (Q)
start: D=x ? start:got0;
got0: D=x ? start:got00;
got00: D=x ? got001:got0;
got001: D=x ? start:got0010;
got0010: D=x ? start:got00;
default: D=3'bxxx;
endcase
end
always @ (posedge clock)
begin
if(reset)
Q=D;
else
Q=0;
end
//output logic
always @ (Q)
y=Q[2];
endmodule
module testbench;
reg x;
reg clock;
reg reset;
wire y;
wire [2:0]Q;
// Instantiate the module
sequence instance_name (
.x(x),
.clock(clock),
.reset(reset),
.y(y),
.Q(Q)
);
always #100
clock=~clock;
//input data bit
initial begin
clock=1; x=0; reset=0; #200
x=0; reset=0; #200
x=0; reset=0; #200
x=1; reset=0; #200
x=0; #200
x=0; #200
x=1; #200
x=0; #200
x=0; #200
x=1; #200
x=0; #200
$stop;
end
endmodule
module shiftres(w, clock, Q);
input w;
input clock;
output [1:8]Q;
reg [1:8]Q;
always @(posedge clock) //Shift Resistor logic start
begin
Q[8]<=w; // Value of w count as Q[8]
Q[7]<=Q[8]; //Value shifted from Q[8] to Q[7]
Q[6]<=Q[7]; //Value shifted from Q[7] to Q[6]
Q[5]<=Q[6]; //Value shifted from Q[6] to Q[5]
Q[4]<=Q[5]; //Value shifted from Q[5] to Q[4]
Q[3]<=Q[4]; //Value shifted from Q[4] to Q[3]
Q[2]<=Q[3]; //Value shifted from Q[3] to Q[2]
Q[1]<=Q[2]; //Value shifted from Q[2] to Q[1]
end
endmodule
module testbench;
reg w, clock;
wire [1:8]Q;
// Instantiate the module
shiftres instance_name (
.w(w),
.clock(clock),
.Q(Q)
);
always#100
clock=~clock;
initial begin
clock=1; w=1; #200
w=0; #200
w=1; #200
w=0; #200
w=0; #200
w=1; #200
w=1; #200
w=0; #200
$stop;
end
endmodule
module fulladder(x0, x1, x2, x3,cin,c, y0, y1, y2, y3, s0, s1, s2, s3);
input x0, x1, x2, x3; //Four bit input X
input y0, y1, y2, y3; //Four bit input Y
input cin; //Carry input
output c; //Carry output
output s0,s1,s2,s3; //Sum output
wire s10,s20,s30,s40,c10,c11,c0,c20,c21,c1,c30,c31,c2,c40,c41; //Intermediate nodes
xor V1(s10,x0,y0); // x0 xor y0 = s10
xor V2(s0,s10,cin); // s10 xor cin = s0
and V3(c10,x0,y0); // x0 and y0 = c10
and V4(c11,s10,cin); // s10 and cin = c11
or V5(c0,c10,c11); // c10 or c11 = c0
xor V6(s20,x1,y1);
xor V7(s1,s20,c0);
and V8(c20,x1,y1);
and V9(c21,s20,c0);
or V10(c1,c20,c21);
xor V11(s30,x2,y2);
xor V12(s2,s30,c1);
and V13(c30,x2,y2);
and V14(c31,s30,c1);
or V15(c2,c30,c31);
xor V16(s40,x3,y3);
xor V17(s3,s40,c2);
and V18(c40,x3,y3);
and V19(c41,s40,c2);
or V20(c,c40,c41);
endmodule
`timescale 1ns/1ns
module testbench;
reg x0, x1, x2, x3, x0, x1, x2, x3, cin; // Inputs
wire c,s0,s1,s2,s3; // Outputs
// Instantiate the module
fulladder instance_name (
.x0(x0),
.x1(x1),
.x2(x2),
.x3(x3),
.y0(y0),
.y1(y1),
.y2(y2),
.y3(y3),
.cin(cin),
.c(c),
.s0(s0),
.s1(s1),
.s2(s2),
.s3(s3)
);
initial begin
x0=0; x1=0; x2=1; x3=1; y0=1; y1=1; y2=0; y3=0; cin=0; #250;
x0=1; x1=0; x2=0; x3=0; y0=0; y1=0; y2=1; y3=0; cin=1; #250;
x0=1; x1=1; x2=1; x3=1; y0=1; y1=0; y2=1; y3=1; cin=1; #250;
x0=1; x1=0; x2=0; x3=1; y0=0; y1=1; y2=0; y3=0; cin=1; #250;
$stop;
end
endmodule
Right click to the folder that you want to hide and select Properties. From the Customize tab Click Change Icon. Select 51 number Icon that will find at 12th column of %SystemRoot%\system32\SHELL32.dll. Then select Ok > Ok. Rename the folder and type Alt+0160 and press enter. You will see that your folder is vanished. Change the views as List. To open press Ctrl+A, a little highlighted shadow will appear over the hiden forder. Double click to open.